Intel and AMD Push x86 Forward with New Improvements
Two of the technology industry’s stalwarts, Intel and AMD, are advancing the x86 ecosystem to stay competitive as Arm and RISC-V expand their footprints. A year after forming the x86 ecosystem advisory group (EAG), the two companies are reporting concrete results: new instructions that harden security, accelerate vector and matrix workloads, and modernize the interrupt and memory-safety model. The collective effort aims to keep the x86 Instruction Set Architecture (ISA) relevant in a multi-ISA landscape.
FRED: A Modernized interrupt model to reduce latency
The first notable addition is FRED (Flexible Return and Event Delivery), a new instruction intended to standardize and streamline interrupt handling. By offering a modernized interrupt model, FRED targets lower latency in software and improved reliability. The goal is to provide a consistent mechanism for handling events and returns across various software stacks, helping operating systems, runtimes, and drivers become more responsive in complex systems where latency can be a bottleneck.
AVX10 and ACE: Boosting vector and matrix performance
Beyond interrupt enhancements, the EAG members have standardized and implemented AVX10 and ACE (Advanced Matrix Extensions for Matrix Multiplication) across the stack. AVX10 extends the already-robust vector processing capabilities of x86, enabling wider, more capable 512-bit vector operations. ACE is designed to accelerate matrix multiplication, a cornerstone of scientific computing, AI inference, and data analytics, with extended precision and throughput. This coordinated standardization means developers can target these new capabilities with a consistent set of tools and compiler support, reducing porting costs and enabling more predictable performance gains across CPUs from different vendors.
ChkTag: Hardware-assisted memory safety
Perhaps the most consequential update is ChkTag, a memory-tagging instruction set that attaches small tags to memory and checks them in hardware. ChkTag helps catch common memory-safety bugs such as buffer overflows and use-after-free errors. By giving developers and compilers fine-grained control over where tags are checked, this approach reduces the overhead of software-only protections while enabling robust hardening of applications, kernels, hypervisors, and firmware. Importantly, binaries compiled with ChkTag support can still run on older processors that lack the hardware features, easing deployment and transition paths. The designers envision ChkTag as a complementary defense to Shadow Stacks and confidential computing, with a full specification expected later in the year.
The x86 EAG’s direction and historical context
The emergence of the x86 ecosystem advisory group marks a shift from older experiments toward a practical, production-oriented roadmap. After forming the EAG, Intel moved away from its x86S initiative, which aimed to simplify processor design by trimming legacy compatibility. The current effort acknowledges the sprawling heritage of x86—from the original 8086 to 16-bit, 32-bit, and now 64-bit x86-64—while seeking to introduce vector, matrix, and security-oriented enhancements that can be adopted broadly. The objective is not to abandon legacy support but to evolve it in a way that makes the ISA safer and more capable without creating a fragmentation nightmare for developers or end-users.
Industry implications and deployment paths
With AVX10, ACE, and ChkTag, developers and system architects gain practical tools to improve performance and security across a broad set of workloads. The hardware-assisted memory tagging of ChkTag, in particular, could influence kernel design, virtualization strategies, and firmware security practices, all while maintaining backward compatibility. Since ChkTag-enabled binaries can run on older hardware, the update lowers barriers to adoption and provides an incremental path toward broader hardware-enforced safety. In tandem with FRED, these changes could yield lower latency in interrupt-heavy workloads and more deterministic performance in real-time and latency-sensitive environments.
Outlook: A collaborative, multi-vendor evolution
Intel and AMD’s collaborative stance in shaping x86’s future reflects a pragmatic balance between preserving legacy compatibility and embracing modern hardware features. While Arm and RISC-V continue to gain traction in certain segments, x86 remains deeply embedded in desktops, servers, and enterprise applications. The arrival of FRED, AVX10, ACE, and ChkTag signals a continued commitment to scaling performance and hardening the ecosystem. The next steps will likely focus on tooling, compilers, and platform firmware adaptations that make these features accessible to developers and end-users alike.
Sources: Intel, AMD
